| 摘要 |
PROBLEM TO BE SOLVED: To reduce the layout area of a phase synchronization delay circuit. SOLUTION: A delay buffer 200 delays an outside system clock only in a first delay time. A main delay part 210 delays the output from the delay buffer only in a prescribed second delay time or bypasses it as it is, according to a flag signal. A delay line 240 successively delays the output of the main delay part in each unit time. A phase synchronization detecting means 250 detects a third delay period necessary for synchronizing the output of the main delay part with the output of the delay buffer according to the flag signal by using an output from the delay line 240 and outputs an enable signal. A flag signal generator 260 makes the flag signal active, only when a phase comparison detecting means detects the third delay period. A switching part 230 is controlled by enable signal, so that the switching of a pertinent signal among signals outputted from the delay line can be switched. A clock driver outputs an internal clock delayed by a prescribed time. |
