| 摘要 |
<p>A recovery circuit (930) for recovering the control gate and the channel well of a floating gate memory cell to a first recovery potential and a second recovery potential respectively after a program or erase process has been performed on the cell is provided. The floating gate memory cell may include the control gate (80) coupled to a first node (702) at a first program/erase potential, a floating gate (76), the channel well (64) coupled to a second node (704) at a second program/erase potential having a first conductivity type, and drain (88) and source (72) regions within the channel well (64) having a second conductivity type different from the first. The recovery circuit (930) includes control circuitry that provides a recovery control signal indicating when the program or erase process has been completed, and a coupling circuit that connects the control gate (80) to the channel well (64) in response to the recovery control signal.</p> |
