| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of phase comparison till a state becomes lock-on before starting the normal operation of a DLL(delay locked loop) circuit. SOLUTION: A clock CLK is fetched by an input buffer 10 and a first clock c-clk is outputted and supplied to variable delay circuits 11 and 13 and a phase comparing circuit 16. Then, the clock c-clk 2 outputted from the variable delay circuit 13 passes through a dummy data output buffer 14 and a dummy input buffer 15 so as to be supplied to the phase comparing circuit 16 as the second clock d-i-clk. The phase difference of the first and the second clocks is detected by the phase comparing circuit 16 and phase comparing signals ϕSO-ϕRE, ϕSS and ϕRR. First and second delay control circuits 17 and 18 supply delay control signals ϕE-1-ϕE-32 to the variable delay circuits 11 and 13. In result, the delay quantities of the circuits 11 and 13 are controlled so as to permit the phases of the first and the second clocks to coincide each other. |
