发明名称 DRAM AND METHOD FOR ACCESSING DATA OF DRAM
摘要 <p>PROBLEM TO BE SOLVED: To shorten a pre-charging time by providing plural DRAM cells and sense amplifiers respectively in response to plural DRAM cells and activating only the sense amplifier answering to the cell to be accessed among plural DRAM cells. SOLUTION: A DRAM 10 contains a pre-fetch/latch circuit 14, an output buffer 18 connected to the pre-fetch/latch circuit 14 and a pre-load/latch circuit 16 connected to a sense amplifier part 26. Data of 32 pieces of memory cells 20 on a word line 22 are stored in the pre-fetch/latch circuit 14, and the data are read out from the output buffer 18 to four respective outputs. At a writing, the data inputted to plural respective inputs are stored temporarily in the pre- load/latch circuit 16, and when all the 32 pieces of data are inputted, they are written simultaneously in 32 pieces of memory cells 20. The data are pre-loaded to the pre-load/latch circuit 16, and are written back in batch to be automatically pre-charged.</p>
申请公布号 JP2000195253(A) 申请公布日期 2000.07.14
申请号 JP19980370358 申请日期 1998.12.25
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 SUNANAGA TOSHIO;WATANABE SHINPEI
分类号 G11C11/409;G11C7/06;G11C7/10;G11C11/401;G11C11/407;G11C11/4091;(IPC1-7):G11C11/401 主分类号 G11C11/409
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