| 摘要 |
PURPOSE: A semiconductor memory device including a multi bit latch circuit capable of high integration is provided to latch the multi-bit data by reducing the data latch circuit. CONSTITUTION: The semiconductor memory device including the multi bit latch circuit capable of high integration includes at least one memory cells, a bit line, a sense amplifier, a reference node, the first and second latch circuits(210,220), an initializing circuit(240), a logic circuit(230), and the first through third devices(250,260,270). The sense amplifier senses the bit line during the first through third sensing periods. The first and second latch circuits includes input and output nodes and store one bit data, respectively. The initializing circuit is coupled with the output node of the first and second latch circuits and initializes the output node with the reference voltage. The logic circuit combines the first signal representing sensing position and the second signal representing the status of the memory cell and amplified by the sense amplifier. The first device inverts the state of the first latch circuit with response to the third signal during the first sensing period. The second device inverts the state of the second latch circuit with response to the third signal during the second sensing period. The third device restores the state of the first latch circuit to the reference voltage level with response to the third signal during the third sensing period.
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