Pulse control circuit

摘要

A frequency synthesizer or a circuit for deleting cycles from a wave source includes a dual modulus counter responsive to a reference frequency source of the synthesizer or waves of the source. The dual modulus counter selectively decreases the number of cycles of the source by the factors K2 and (K2+1). A frequency divider divides the frequency of the source by a third factor L to derive an output wave. The dual modulus counter is activated so it divides by K2+1, whereby the dual modulus counter derives an output signal having a frequency F0=Fin/K2 (1-1/L), where Fin equals the frequency of the source, L is an integer and K2 is an integer greater than L.