| 摘要 |
<p>PROBLEM TO BE SOLVED: To set the delay time from the input of a code-side storage circuit till the output of a decoding-side accumulation circuit to be constant in spite of a transmission bit rate. SOLUTION: A time adjustment accumulation circuit 3 is provided between the code-side storage circuit 2 and the decoding-side storage circuit 3. When, total delay time generated in the three storage circuits 2, 3 and 7 is set to be Td, the two capacities of the code-side storage circuit 2 to be B1 and a transmission bit rate at the time of an initial operation at the time of the initial operation, the initial data quantity of (Td×BR).B1 =B2 is stored in the time adjustment storage circuit 3. When the transmission bit rate is changed, writing into the time adjustment storage circuit 3 is immediately set to be that based on the new transmission bit rate and the reading of the time adjustment storage circuit 3 is changed to that based on the new transmission bit rate by making itpass through total delay time Td.</p> |
