| 摘要 |
<p>Method and apparatus are disclosed for a low power, high density cell based array structure (10, 15) that permits implementation of designs having compute/drive cell ratios of N:1. The improved performance is provided in part by relocating the substrate (140) and well taps (145) within the compute cell, and in at least some instances by removing the well tap (145) from the drive cell. Further, an extra routing track (85) may be provided by not sharing source/drain areas of adjacent drive cells. Still further, a power mesh (VDD) may be provided which simplifies routing and improves flexibility.</p> |
