发明名称 MULTI-BANK MEMORY WITH ONE READ PORT AND ONE OR MORE WRITE PORTS PER CYCLE
摘要 A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.
申请公布号 EP3089045(A1) 申请公布日期 2016.11.02
申请号 EP20160165279 申请日期 2016.04.14
申请人 MARVELL ISRAEL (M.I.S.L) LTD. 发明人 BROMBERG, DROR;SHERMAN, ROI
分类号 G06F13/16 主分类号 G06F13/16
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