发明名称 PACKET PROCESSOR AND SEQUENCE CONTROL METHOD
摘要 <p>PROBLEM TO BE SOLVED: To provide a packet processor in a simple configuration capable of shortening a processing time and a sequence control method. SOLUTION: This packet processor is provided with a receiving part 100 for receiving an input packet, and for outputting it to any of a plurality of packet outputting terminals based on a signal to be inputted from the outside, a plurality of packet processing parts 110-1-110-4 for operating prescribed processing to the input packet, and for outputting the processed packet, an output part 120 for inputting the processed packet to each of its input terminals, and for outputting the packet based on a control signal to be applied from the outside and a sequence control part 130 for supplying the control signal to the output part. When the output path of the processed packet to be outputted from any of those packet processing parts is made different from the output path of the input packet which is being processed by another packet processing part whose previously started processing is not completed, the sequence control part generates the control signal to output the packet from the output part.</p>
申请公布号 JP2003078557(A) 申请公布日期 2003.03.14
申请号 JP20010267037 申请日期 2001.09.04
申请人 NEC CORP 发明人 UENO YOJI
分类号 H04L12/701;H04L12/771;(IPC1-7):H04L12/56 主分类号 H04L12/701
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