Parity detection circuit for programmable logic systems - has multiple inputs and outputs with control memory buffer store and flip-flop

摘要

A coefficient register is connected to a programmable control memory and through a buffer store to a flip-flop, an accumulator, up-down counter and a parity detector. A parity generator is connected to the input/output circuits and associated parity registers. a micro programmer controlled by a clock generator via a counter provides sequential control pulses for the rest of the circuit. Reference signals from the input/output circuits feed a parity generator whose output is connected with that of input/output registers. A comparator connected to the accumulator and address gives a control pulse to modify the contents of the parity registers.