Reduced generation of second harmonics of FETs

摘要

A structure and method for reducing second-order harmonic distortion in FET devices used in applications that are sensitive to such distortion, such as switching RF signals. The asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb of a FET device are equalized by adding offsetting capacitance or a compensating voltage source.

主权项

1. A field effect transistor device having reduced second-order harmonic distortion, including:
(a) a drain region, a source region, and a gate arranged on a body such that the gate modulates a conductive channel between the source region and the drain region; and (b) an added capacitive layer overlaying but insulated from the source region and the drain region, and directly coupled to the body and capacitively coupled to the source region and the drain region, and sized to set the total capacitance from the source region to the body to be essentially equal to the total capacitance from the drain region to the body, wherein the added capacitive layer is arrayed symmetrically with respect to the X-Y axes of the field effect transistor device.