Non-volatile memory unit and method for manufacturing the same

摘要

A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.

主权项

1. A method for manufacturing a non-volatile memory unit, comprising the steps of:
(1) providing a substrate; (2) forming a first base dielectric layer on the substrate; (3) forming a sacrificial layer on the a first base dielectric layer; (4) defining a first pattern opening and a second pattern opening at the first base dielectric layer and the sacrificial layer; (5) performing ion implantation according to the first pattern opening; (6) selectively changing the thickness of the first base dielectric layer in order to form damascene grooves that spaced apart along the horizontal direction; (7) forming a first polycrystalline silicon layer on the first base dielectric layer and the first polycrystalline silicon layer is formed in the damascene grooves; (8) forming a covering dielectric layer on the first polycrystalline silicon layer; (9) forming a second base dielectric layer on the substrate, and the first polycrystalline silicon layer and the covering dielectric layer together form a sidewall dielectric layer; (10) forming a second polycrystalline silicon layer to fill spaces that extends along the horizontal direction between the first polycrystalline silicon layer and the sidewall dielectric layer; (11) forming a coupled dielectric layer on the second polycrystalline silicon layer, the sidewall dielectric layer and the covering dielectric layer; (12) selectively forming a third polycrystalline silicon layer on the coupled dielectric layer; and (13) defining a third pattern opening and performing ion implantation.