A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor.
申请公布号
NO842747(A)
申请公布日期
1985.01.08
申请号
NO19840002747
申请日期
1984.07.05
申请人
HONEYWELL INFORMATION SYSTEMS INC,
发明人
HOOKER, LANE K.,;HOWELL, THOMAS H.,;FERRELL, CHARLES W.,