发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To provide conventionality and redundancy to the titled circuit by constituting a decision circuit deciding whether or not an extracted signal is a correct frame synchronizing signal, and a counter circuit judging out of frame synchronism of a microprocessor. CONSTITUTION:A data signal from an input terminal 1 is fed to a frame synchronizing signal extraction circuit 4 and a frame synchronizing signal detecting circuit 5 via a serial/parallel converting circuit 3. A CPU circuit 8 decides whether or not the signal extracted by the frame synchronizing signal extracting circuit 4 is a correct frame synchronizing signal, counts its decided output, and judges whether the frame synchronization is established or released depending on the counted result.</p>
申请公布号 JPS60219835(A) 申请公布日期 1985.11.02
申请号 JP19840076282 申请日期 1984.04.16
申请人 NIPPON DENKI KK 发明人 MATSUOKA ISAO
分类号 H04L7/08;H04L7/04 主分类号 H04L7/08
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