Semiconductor chip memory array - features memory cell pairs each comprising FET and stacked cell capacitor

摘要

The semiconductor chip has an arrangement of memory cell pairs, each comprising a FET (16d) and a stacked cell capacitor. One active area (22e) is common to both transistors and is located between, and at right angles to, a pair of parallel word lines (18, 20), while the other transistor active regions (24d, 26d) lie on opposite sides of the word lines. The transistor and wordline structure is covered with an isolating dielectric layer over which a bit line (28d) is fabricated. The outer active regions connect the stacked capacitor cells via buried connectors that drop through openings in the dielectric layer (32, 34), while the extension (58) of the common active region under the bit line is connected to the latter via a third buried contact and associated opening (62). ADVANTAGE - Increased memory cell packing density.