| 摘要 |
A data transfer mechanism is provided between a host device and a slave device in which the slave bus width is automatically configured according to mode information, and the exact number of slave cycles required are generated according to the host request. In particular, a bus interface controller interfaces a host device having a host bus of a predetermined physical bus width to a slave device having a slave bus of a variable one of multiple possible logical bus widths, where the host device physical bus width in bits is an integer multiple of the slave device logical bus width in bits. First circuitry is responsive to a request from the host device for exchanging handshaking signals with the slave device to execute a number of slave bus transfer cycles until a last cycle signal has been received, and for returning a completion signal to the host device. Second circuitry is responsive to mode-related signals and byte enable signals from the host device for generating the last cycle signal for the first circuitry. Together, the first circuitry and the second circuitry therefore implement what may be termed a "checking-and-moving" scheme. That is, the first circuitry continues to interact with the slave device to execute data transfer cycles until the first circuitry receives a last cycle signal from the second circuitry, which continually checks to see if the present cycle is the last cycle. The resulting data transfer mechanism is conceptually simple, scalable, and easy to implement.
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