发明名称 Product-sum operation unit
摘要 A product-sum operation unit including a multiplying unit, a pipeline register for loading a multiplication result, an adder unit for adding a summand and either an output of the pipeline register or an addend. A timing signal generating unit generates first and second timing signals (T1, T2) that are synchronized with first and second clocks (CK1, CK2). A first instruction latch loads an instruction synchronously with the first timing signal (T1) to output a first control signal. A second instruction latch loads an instruction loaded in the first instruction latch synchronously with the second timing signal (T2) to output the second control signal. A control signal selector outputs the second control signal in response to the first timing signal (T1), and also outputs the first control signal to the adder unit, in response to the second timing signal (T2).
申请公布号 US5424969(A) 申请公布日期 1995.06.13
申请号 US19930013798 申请日期 1993.02.05
申请人 FUJITSU LIMITED;FUJITSU VLSI LIMITED 发明人 YAMADA, KENJI;IGA, KIICHIRO;SAWADA, MASARU
分类号 G06F7/544;(IPC1-7):G06F7/00 主分类号 G06F7/544
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