| 摘要 |
A new and unique method of performing operand increment in a Booth recoded multiply array. Use of the new method allows operands to be incremented without adding any delay to the multiply array. Added hardware is minimal and requires very little surface area on an IC. The method comprises partitioning a multiplier into overlapping groups of N bits, wherein a first of a number of multiplier partitions comprises the multiplier's least significant bits, and a placeholder bit of less significance than the multiplier's least significant bits. The placeholder bit is set to a logic "1" when desiring to increment the multiplier. Multiples of a multiplicand are generated. Generation of even multiples necessitates shifts of the multiplicand. Bit vacancies created during these shifts are filled with logic "1"s when desiring to increment the multiplicand. Multiplicand multiples are then inverted. The multiplicand increment bit is exclusively ORed with the sign bit of each of the generated multiplicand multiples, and the outputs of the exclusive OR gates are added to the least significant bit positions of respective multiplicand multiples. Operation of the multiply array is otherwise similar to the operation of a standard Booth recoded multiply array.
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