| 摘要 |
PROBLEM TO BE SOLVED: To improve the access efficiency of" a graphic memory and improve the picture quality of a enjoying picture on a memory integrated type graphic, display device by controlling display access by the graphic processor adaptively to the cache mode of' a CPU. SOLUTION: Of the memory integrated type graphic display device wherein the CPU 10 and graphic processor 20 accesses the common graphic memory 40, the graphic processor 20 is provided with a bit specifying the cache system of the CPLI 10 and according to this specification, the time of' single-time maximum display access is varied. Namely, when a copy-back system is adopted, write access by the CPU is shorter than that of' a store-through system, so the display access time of the graphic processor 20 is shortened. |
