Method and apparatus for improving the speed of a logic circuit

摘要

The invention is disclosed as embodied in a data processing system circuit for outputting a signal based on an evaluation of input signals coupled to the circuit. The circuit has a number of transistors configured so that the output signal is triggered by a triggering combination of input signals. The circuit also has a discharge transistor coupled to a signal for switching the discharge transistor to a state tending to discharge a node in the circuit. The node must be discharged to a certain level to trigger the output signal, so that discharging the node after it has become charged up above the certain level tends to reduce evaluation time for the circuit.