| 摘要 |
PURPOSE: An apparatus for testing a memory cell is provided to store data to reduce a test time for a memory cell by using a redundancy array in order to store data to a sub bit line for redundancy. CONSTITUTION: A redundancy array(20) for redundancy memory cell is connected with a normal array(10) of a structure of hierarchical bit line in order to perform a memory repair operation. A switching portion(30) is used for connecting a sub bit line(RSBL) of the redundancy array(20) for redundancy memory cell with a bit line(BL) of the normal array(10). The switching portion(30) stores the same as data of the sub bit line(RSBL) or the data of opposite polarity to the data of the sub bit line(RSBL) by changing a voltage level of a particular bit of input addresses in an input process of an active command.
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