| 主权项 |
1. A signal transmission circuit suitable for DDR, adapted to drive a connecting pad, said signal transmission circuit comprising:
a level shifting circuit, comprising:
an up level shifter;a down level shifter; andwherein, the up level shift and the down level shifter are disposed between a DDR operating voltage and a ground voltage, receive an input signal, and correspondingly output a first shift signal and a second shift signal, respectively; the input signal comprises a first operating voltage and a second operating voltage, the first operating voltage is equal to the ground voltage, and the second operating voltage is smaller than the DDR operating voltage; a buffer circuit, comprising:
an up buffer unit, disposed between the DDR operating voltage and a first reference voltage, coupled to an output of the up level shifter to receive the first shift signal and to output a first logic signal according to the first shift signal; anda down buffer unit, disposed between the ground voltage and a second reference voltage, coupled to an output of the down level shifter to receive the second shift signal and to output a second logic signal according to the second shift signal; an output circuit, comprising:
a pull-up circuit, coupled between the DDR operating voltage and the connecting pad, further coupled to the up buffer unit to selectively output the DDR operating voltage to the connecting pad according to the first logic signal; anda pull-down circuit, coupled between the ground voltage and the connecting pad, further coupled to the down buffer unit to selectively output the ground voltage to the connecting pad according to the second logic signal; wherein, the up level shifter and the down level shifter adopt input and output (IO) devices to respectively output the first shift signal and the second shift signal; the up buffer unit, the down buffer unit, the pull-up circuit and the pull-down circuit adopt core devices; the second reference voltage is equal to the second operating voltage, and the first reference voltage is a difference between the DDR operating voltage and the second reference voltage, wherein the up level shifter comprises: a 1st inverter; a 2nd inverter; a 3rd inverter; a 4th inverter; and a 5th inverter; wherein, the 1st to 5th inverters are disposed between the first operating voltage and the second operating voltage of the input signal, the 1st inverter has its input end coupled to the input signal, the 1st, 2nd and 3rd inverters are connected in series to output an inverted signal of the input signal, the 4th inverter has its input end coupled to an output end of the 2nd inverter to cause the 1st, 2nd, 4th and 5th inverters to be connected in series to output a non-inverted signal of the input signal; an 11th switch element, comprising a control end, a first path end and a second path end, the 11th switch element having its control end coupled to an output end of the 3rd inverter to receive the inverted signal of the input signal, and its first path end coupled to the ground voltage; a 12th switch element, comprising a control end, a first path end and a second path end, the 12th switch element having its control end coupled to an output end of the 5th inverter to receive the non-inverted signal of the input signal, and its first path end coupled to the ground voltage; a 13th switch element, comprising a control end, a first path end and a second path end, the 13th switch element having its control end coupled the control end of the 12th switch element and the output end of the 5th inverter to receive the non-inverted signal of the input signal, and its first path end coupled to the second path end of the 12th switch element; a 14th switch element, comprising a control end, a first path end and a second path end, the 14th switch element having its control end coupled to the second reference voltage, its first path end coupled to a connecting node between the second path end of the 12th switch element and the first path end of the 13th switch element, and its second path end coupled to the second path end of the 13th switch element; a 15th switch element, comprising a control end, a first path end and a second path end, the 15th switch element having its first path end coupled to the DDR operating voltage, its second path end and control end coupled together and further coupled to the second path end of the 11th switch element, wherein a connecting node between the second path end of the 15th switch element and the second path end of the 11th switch element is defined as a first node; a 16th switch element, comprising a control end, a first path end and a second path end, the 16th switch element having its control end coupled to the first node, its first path end coupled to the DDR operating voltage; a 17th switch element, comprising a control end, a first path end and a second path end, the 17th switch element having its control end coupled to the first node, and its path end coupled to the second path end of the 16th switch element; an 18th switch element, comprising a control end, a first path end and a second path end, the 18th switch element having its control end coupled to the first reference voltage, its first path end coupled to a connecting node between the first path end of the 17th switch element and the second path end of the 16th switch element, its second path end coupled to the second path end of the 17th switch element and further coupled to the second path end of the 13th switch element and the second path end of the 14th switch element, wherein a connecting node between the second path end of the 18th switch element, the second path end of the 17th switch element, the second path end of the 13th switch element and the second path end of the 14th switch element is defined as a second node; a 19th switch element, comprising a control end, a first path end and a second path end, the 19th switch element having its control end coupled to the second node, and its first path end coupled to the DDR operating voltage; and a 20th switch element, comprising a control end, a first path end and a second path end, the 20th switch element having its control end coupled to the second node, its first path end coupled to the first reference voltage, and its second path end coupled to the second path end of the 19th switch element, wherein a connecting node between the second path end of the 20th switch element and the second path end of the 19th switch element serves as the output end of the up level shifter to output the first shift signal; wherein, the 11th, 12th, 13th, 14th and 20th switch elements are second-type switch elements, the 15th, 16th, 17th, 18th and 19th switch elements are first-type switch elements, and a type of the first-type switch elements is opposite a type of the second-type switch elements. |
