发明名称 Method and apparatus for phase-lock in a field programmable gate array (FPGA)
摘要 An apparatus for performing phase-lock in a field programmable gate array includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal. A method for performing phase-lock in a field programmable gate array includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal.
申请公布号 US6675306(B1) 申请公布日期 2004.01.06
申请号 US20000523449 申请日期 2000.03.10
申请人 RICOH COMPANY LTD. 发明人 BAXTER MICHAEL A.
分类号 G06F1/12;(IPC1-7):G06F1/12 主分类号 G06F1/12
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