METHOD FOR FABRICATING FERROELECTRIC RANDOM ACCESS MEMORY WITH MERGED-TOP ELECTRODE-PLATELINE CAPACITOR,申请号KR20030043089-传众专利搜索

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发明名称	METHOD FOR FABRICATING FERROELECTRIC RANDOM ACCESS MEMORY WITH MERGED-TOP ELECTRODE-PLATELINE CAPACITOR
摘要
申请公布号	KR100531462(B1)	申请公布日期	2005.11.28
申请号	KR20030043089	申请日期	2003.06.30
申请人		发明人
分类号	H01L27/10;H01L21/00;H01L21/02;H01L21/8242;H01L21/8246;H01L27/115;(IPC1-7):H01L27/10	主分类号	H01L27/10
代理机构		代理人
主权项
地址

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