Channel control circuit and semiconductor device having the same

摘要

A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal.

主权项

1. A semiconductor device, comprising:
a plurality of channels; and pads shared by the plurality of channels, wherein, the plurality of channels are configured to be selectively inputted a clock signal in response to test mode signals for a test operation in a Direct Access mode for simultaneously testing the plurality of channels using the pads.