| 摘要 |
<p>Method of and apparatus for checking the geometry of multi-layer patterns (f, g) for IC structures having identical functions, each of the multi-layer patterns including layer patterns arranged in different level layers, wherein electrical image signal corresponding to any two of the multi-layer patterns and having more than two levels are registered (15, 18-20; 30) with each other and then compared (21; 31) to determine unmatched and matched portions. The comparison of the registered electric image signals may be performed with respect to their amplitude or their gradients. The registration and comparison of two electric image signals may be repeated for all of the layer patterns, with the matched portions being no longer subjected to the registration and comparison (24). A defect detection signal is produced from finally unmatched portions, if any, of the electric image signals having undergone the said registration and comparison.</p> |
