GATE DRIVE CIRCUIT AND DISPLAY DEVICE

摘要

An embodiment of the present invention discloses a gate drive circuit comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal, a logic turn-on input terminal, a logic turn-on output terminal, a control module, a first gating module and a second gating module. An embodiment of the present invention also provides a display device comprising the gate drive circuit. A gate drive circuit with interlaced output is realized, ensuring no suspended state in time sequence between interlaced lines, while maintaining an original dual time sequence (i.e., eliminating suspended state between interlaced lines, and ensuring a stable output of the shifting register).

主权项

1. A gate drive circuit comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal, a logic turn-on input terminal, a logic turn-on output terminal, a control module, a first gating module and a second gating module;
the control module is connected to the high level terminal, the first clock terminal, the second clock terminal, the logic turn-on input terminal, the first gating module and the second gating module; the first gating module is connected to the low level terminal and the gate output terminal; the second gating module is connected to the low level terminal and the logic turn-on output terminal; a logic turn-on output terminal of a present unit circuit is connected with a logic turn-on input terminal of a unit circuit having an interval of one stage with the present unit circuit; the gate output terminal is connected to a gate line; the control module is used for based on the first clock terminal, the second clock terminal, and the logic turn-on input terminal, controlling the first gating module to gate a high level signal from the high level terminal to the gate output terminal; or, gate a low level signal from the low level terminal to the gate output terminal; the control module is also used for based on the first clock terminal, the second clock terminal, and the logic turn-on input terminal, controlling the second gating module, such that: only when the first clock terminal is in an effective time sequence state, the second gating module gates a low level signal from the low level terminal to the logic turn-on output terminal, the low level signal then being transmitted to the logic turn-on input terminal of the unit circuit having an interval of one stage with the present unit circuit, to turn on interlaced output; in other time sequence state, the second gating module gates a high level signal from the high level terminal to the logic turn-on output terminal.