| 摘要 |
<p>A memory register file array addressable in both word and doubleword format has memory cells of a feedback-type latch variety, having at least two tri-state inverter paths (WP1 and WP2) for the input of data, and at least two tri-state inverter paths (RP1, RP2 and RP3) for the output of data. A tri-state inverter (53) provides the feedback within each array cell. This feedback inverter is tri-stated during each write operation, thus increasing circuit speed and permitting simultaneous read and write operations to be performed on the same cell during a single machine cycle. Error correction is performed during format decode and format operations so that error correction code (ECC) syndrome bit generation can occur in parallel with formatting. Improved clocking operations maintain symmetry of the register file clock signals and provide high clock skew tolerance. Tri-state isolation buffers (4, 5, 6, 7, 8 and 9) are used to reduce read access time.</p> |
