| 摘要 |
<p>A data processing system (20') includes a data processor (21) such as a digital signal processor (DSP) and a memory system (22'). The DSP (21) has two data paths for fetching operands from locations specified by two addresses, which may be required for an operation such as a multiply. A fetch from the second data path is delayed in response to a wait signal. The memory system (22') includes at least two memory portions (24, 25). Data from the two memory portions (24, 25) is multiplexed onto the two data paths in response to a first portion of the respective addresses. If the first portions of both addresses are equal, then if second portions are unequal, the wait signal is activated. If the second portions of the addresses are equal, such as during a square operation, the wait signal is inactive and data is simultaneously read by both data paths. <IMAGE></p> |
