MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING

摘要

A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.

主权项

1. A circuit comprising:
a bias circuit for a biased transistor, the bias circuit including a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to a gate of the biased transistor and configured to provide a bias voltage, wherein the reference transistor has a first transconductance substantially identical to a second transconductance of the biased transistor, wherein the gate of the biased transistor receives an additional input signal.