| 摘要 |
A phase locked loop circuit comprising a reference counter, a programmable counter, a phase detector and a lock detector. The phase locked circuit further comprises a lock enable unit for controlling a voltage pump under control of the phase detector, a channel selector for selecting a desired channel according to a user's selection, a lock holder for holding a locked state in response to an output signal from the channel selector and a lock signal from the lock detector, a refresh clock generator for generating a refresh clock signal in response to an output signal from the reference counter, a NAND gate for NANDing an output signal from the lock holder and the refresh clock signal from the refresh clock generator and outputting the resultant signal to the lock enable unit, first and second inverters for inverting the output signal from the NAND gate, respectively, a first transistor for passing the reference signal to a ground terminal in response to an output signal from the first inverter, and a second transistor for passing the voltage controlled oscillating signal to the ground terminal in response to an output signal from the second inverter.
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