| 摘要 |
<p>A method and apparatus adapted for glitchless switching between unrelated clock signals is achieved using simple AND/OR logic gates to form the circuit that synchronizes the clock inputs. In an example embodiment of the present invention, two clock signals are generated along with a select input signal capable of deselecting one of the clock signals and delaying selection of the second clock input signal. The first and second clock signals and the select input signal are multiplexed to generate a multiplexed output clock signal corresponding to one of the input clock signals. A selection delay is generated between the deselection of the first clock signal and the selection of the second clock signal that is longer than the low pulse width of the minimum low pulse width of the first clock signal and the low pulse width of the second clock signal, such that switching between clock signals will not create a glitch at the multiplexed output.</p> |
