发明名称 MEMORY SYSTEM
摘要 A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
申请公布号 US2017109274(A1) 申请公布日期 2017.04.20
申请号 US201615291834 申请日期 2016.10.12
申请人 SK hynix Inc. 发明人 LEE Do-Yun;KIM Min-Chang;KIM Chang-Hyun;LEE Yong-Woo;LEE Jae-Jin;JUNG Hoe-Kwon
分类号 G06F12/02;G06F12/06 主分类号 G06F12/02
代理机构 代理人
主权项 1. A memory system comprising: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices, wherein the first and second memories are separated from the processor, wherein the processor accesses the second memory device through the first memory device, wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal, wherein the first memory controller includes a plurality of channel controllers respectively corresponding to the plurality of first memories, and suitable for controlling data communication between the processor and a selected one among the plurality of first memories through processor channels and data communication between two or more selected ones among the plurality of first memories through a memory link different from the processor channels, and wherein the plurality of channel controllers control the two or more selected first memories to perform the data communication directly with one another of the two or more selected first memories through the memory link in response to memory link commands provided from the processor for the two or more selected first memories.
地址 Gyeonggi-do KR