| 摘要 |
PURPOSE:To generate an abnormality signal of high response in the event of program abnormality by performing detection of IST abnormality, machine cycle abnormality and address abnormality at every instruction IST. CONSTITUTION:A detection signal P is generated from a microcomputer muCM10 via a gate 7 by an IST fetch synchronizing signal F and a machine cycle MC synchronizing signal M. The IST is sent to an IST nonregistration detecting circuit 1, by which it is collated with the ISTs having been registered. In the event of noncoincidence, an IST nonregistration signal D is emitted and an MC number signal N is also outputted. The signals D and P generates an IST abnormality signal E3 via a gate 6. The signal N is applied to an MC number noncoincidence detecting circuit 2, where the signal N is latched at the timing of the signal P. When the signals M and N differ, an M number noncoincidence signal I is transmitted therefrom and an MC number abnormality signal E1 is outputted via a gate 3. An address is inputted to an address limiter 4, and when it exceeds a predetermined access range, an address range deviation signal L is transmitted, and an address abnormality signal E2 is outputted via a gate 5. |
