| 摘要 |
Bit sequences combined to form transmission blocks of a particular length arrive in a receiving and evaluating device ES via several parallel lines of different length, the individual bits being sent in a fixed time frame. For the parallel evaluation of the bit information, the different length of the individual lines L1 to Ln is to be equalised without special circuit measures having to be taken in each receiving and evaluating device ES. By allocating one shift register (SR1 to SRn) per line (L1 to Ln) and sampling the lines with a pulse series which is within the time frame, the sampling results present per line can be picked up in parallel at the output of the shift registers. In addition, bits which are too long or too short can be eliminated by means of a particular selection of the sampling pulses becoming effective. <IMAGE> |
