| 摘要 |
<p>PURPOSE:To compensate out-of-synchronism at a receiving circuit, by comparing a start bit of a start-stop signal with a start bit delayed from it by N-word so as to detect a failure in the start bit. CONSTITUTION:An ST detecting circuit 18 outputs a signal without the start bit ST when the start bit ST of a receiving data receives a erroneous signal in error. The resulted signal is received at a 2-word delay circuit 6 and a signal delayed by 2-word is outputted to an NOT circuit 7. On the other hand, a signal from the circuit 18 is inverted 13 and inputted to an OR circuit 10, and a signal (d) inverted at the circuit 7 is inputted to an EX-OR circuit 8 and an FF9. The FF9 is reset with the signal (d) and 0 level is inputted to the circuit 10, then the circuit 10 inputs a signal (h) inverting the ST to the circuit 8. The circuit 8 compares the signals (d), (h), sets an FF4' by a 1-level signal (e) via an OR circuit 13 and an NOT circuit 19 when the ST is erroneous, the erroneous point of the ST is held to 1-level with an output, and a signal correcting is transmitted to a receiving circuit after 2-word.</p> |
