| 摘要 |
<p>PURPOSE:To perform clock synchronization with high-precision without increasing the load on each processor by adding an external circuit which compares the operation clocks of respective processors and controlling the supply of a reference clock by the external circuit. CONSTITUTION:A master processor 1 and a slave processor 2 execute respective steps of programs on the basis of a main clock CLK supplied from a clock source 7. The phase comparing circuit 6 compares the phases of the operation clocks FBO and FBOS outputted from both processors 1 and 2, and outputs a gate control signal to an AND gate 7. Consequently, the operation clocks of both processors 1 and 2 rise or fall completely coincidently.</p> |
