| 摘要 |
PURPOSE:To decrease the delay in leading and trailing of a CMOS inverter circuit by increasing or decreasing a resistance of a p-channel transistor (TR) than the resistance of a n-channel TR. CONSTITUTION:The resistance of the p-channel MOS TRs TR1, TR5 is increased more than that of the n-channel MOS TRs TR6, TR2 to bring an input threshold voltage to Vcc/2 or below. When the level of an input IN changes from H to L, an output (b) of the p-channel side inverter rises from L to H, but the leading is unsharpened. An output (c) of the n-channel side inverter rises also from L to H, the level is boosted by the leading of the output (b), the back gate effect is acted on the TR2 to quicken the leading of the output (c). The outputs (b), as above are received by CMOS inverters TRs3, 4 of the next stage, the turn-on of the n-channel TR4 is quickened by the output (c) especially and not too much delay is caused for the leading/trailing at an output OUT. |
