| 摘要 |
PURPOSE:To improve an efficiency in an address converting buffer invalidating processing by information a request for invalidating the address converting buffer generated in one processor to other processor and invalidating the address converting buffer of the processor. CONSTITUTION:An instruction fetched to the instruction fetch circuit 16 of an instruction unit 13 in respective instruction processors 11, 12 is monitored by an address converting buffer (TLB) invalidating request instruction discriminating part 17. When the instruction is the TLB invalidating request instruction, a signal is outputted to a communication control part 19 between the processors, the TLB invalidation of its own is requested to a TLB control part 111 from the control part 19 and a signal for requesting the TLB invalidation is transmitted to other processor. Consequently, the TLB of the processor of its own is invalidated and the TLB of other processor receiving the TLB invalidation request signal is invalidated.
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