Process for producing wells for CMOS-transistor circuits separated by isolation trenches.

摘要

In a double-well CMOS process, in which the wells (5, 12) are separated by isolation trenches (13, 14, 15) made in the substrate (1), the position of the isolation trench (13) along the well edge (12) is defined by an isotropic underetching (7) in an underlying silicon oxide layer (2) used together with a silicon nitride layer (3), which is used as masking layer during the implantation (4) of the well (5) first implanted. The trench (13) itself is produced by anisotropic etching, using as an etching mask the silicon oxide masks (2, 10) used during the well implantations (4, 11). The trench width is determined by isotropic etching (7), and the trench depth is determined by anisotropic etching. In this method, both well implantations (4, 11) and the trench etching (13) are carried out using only one phototechnique; the implantation (11) of the second well (12) and the trench etching (13) are self-adjusting; as a result, minimum n<+> p<+> distances and a space-saving design are possible. The method is used in highly integrated CMOS processes.