| 摘要 |
Data pulses (DATA) are encoded in accordance with a 2,7 run length limited code by a simplified circuit comprising three cascaded flip-flops (33, 34, 35) clocking through the data pulses to provide signals A, B and C and two flip-flops (36, 37) clocking through an intermediate signal Y to provide signals D and E. The signal Y is provided by first NAND gates (40) in accordance with the equation Y = ACDE + BD. The encoded signal X is produced by second NAND gates (41) responsive not only to selected flip-flop outputs but to complementary clock signals (-ESR CLOCK, +ESR CLOCK), in accordance with the equation X = (+ESR GLOCK).(BD) + (-ESR CLOCK).(BCE + ABE). |
