发明名称 |
DENKITEKINIPUROGURAMU*SHOKYOKANONAMOSMEMORI*SERU |
摘要 |
<p>In the electrically alterable read only memory cell a reduction in cell area and an improvement in tolerance allowed for programming and erase voltages is achieved utilizing a diffused control gate (3) having improved capacitive coupling to the floating gate (7) through a thin oxide layer (5) grown on single crystal silicon (1). A thin oxide layer (6) is also grown over the channel area (2). Polyoxide layers (8) and (10) isolate the programming gate (9) from the floating gate (7) and the latter from the erase gate (11). The ratio of thickness between the oxide layers (5) and (6) and the polyoxide layers (8) and (10) is of one to four or five.</p> |
申请公布号 |
JPH0249026(B2) |
申请公布日期 |
1990.10.26 |
申请号 |
JP19810071521 |
申请日期 |
1981.05.14 |
申请人 |
INTAANASHONARU BIJINESU MASHIINZU CORP |
发明人 |
HAIDEN KURAUI KURANFUOODO JUNIA;CHAARUZU RIIBUSU HOFUMAN;JOFUREI BUROONERU SUCHIIBUNSU |
分类号 |
G11C17/00;G11C16/04;H01L21/8247;H01L29/788;H01L29/792 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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