发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To prevent a fault from being repeated by providing separately a fault detecting circuit, deciding a fault to be a light fault, when a fault cannot be detected by the fault detecting circuit and deciding a fault to be a heavy fault, when the fault is detected, and reporting them to a host device. CONSTITUTION:The fault at the time when a read-out operation of a memory device 4 in a processor part 5 is executed in detected, and the fault is reported to a diagnostic processor part 6. The diagnostic processor part 6 switches it to a diagnostic address bus in order to execute diagnostic read-out to the memory device 4, and holds an address in which a fault is generated. Subsequently, by the diagnostic address bus, the address in which the fault is generated is read out, and when the fault is not detected by a fault detecting circuit 10, the diagnostic processor part 6 decides that the fault is a light fault, sends out an initializing instruction to the processor part 5, and on the other hand, when the fault is detected, the diagnostic processor part 6 decides that its fault is a heavy fault, and reports an operation stop to the host device. In such a manner, the fault can be diagnosed without repeating a fault processing at the time when the fault is generated.
申请公布号 JPH03204732(A) 申请公布日期 1991.09.06
申请号 JP19900001778 申请日期 1990.01.08
申请人 NEC ENG LTD 发明人 HIRAYAMA SHUYA
分类号 G06F11/00 主分类号 G06F11/00
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