Method & structure for forming vertical semiconductor interconnection.

摘要

An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure. In one embodiment, the portion of the tape opposite the area to which the integrated circuit die is to be inner lead bonded includes secondary metallization regions. Suitable vias in the tape connect these secondary metallization regions to selected ones of the metallic leads which are to be inner lead bonded to the integrated circuit. In one embodiment of this invention, the secondary metallization areas are fabricated sufficiently large to allow the mounting of additional components, for example chip capacitors used to filter the supply voltages applied to the integrated circuit. A method for forming is also taught.