| 摘要 |
PURPOSE:To simplify hardware to offer the temporary holding circuit of low cost by supplying a clear signal to the reset terminal of a second D-type flip- flop, and setting the output of a second D-type flip-flop as a circuit output. CONSTITUTION:To a clock input terminal of a DFF2, the output 55 of this AND circuit 5 is applied, and a clear signal 40 is set as a reset signal of the DFF2. When the input signal of an input terminal 10 is '1', when a clock signal 30 rises, the Q output 25 of a DFF1 goes to '1'. As a result, when the next clock signal rises, the output 35 of the DFF2 goes to '1' and the output 20 of an AND circuit 3 goes to '1' at time both the Q outputs 25 and 35 of the DFFs 1 and 2 are both '1', it is inverted by an inverter 4, the clock signal 30 being one input of the AND circuits 5 is masked, and comes to a temporary holding state. Such a state is continued until the DFF2 is reset by the clear signal 40. |
