发明名称 TRI-STATE PREVENTION LOGIC CIRCUIT
摘要 The logic circuit prevents the floating of the output line when all outputs are tri-state, and does not have a pull-up resistor. The circuit comprises a number of OR gates (G41-G4n) for logically OR-ing the control signal and the input signal, an AND gate (G4a) for logically AND-ing all outputs of a number of OR gates, and a buffer (G40) connecting with the output of the AND gate.
申请公布号 KR920008260(B1) 申请公布日期 1992.09.25
申请号 KR19900001721 申请日期 1990.02.13
申请人 HYUNDAI ELECTRONICS CO., LTD. 发明人 KWON, YONG - DON
分类号 H03K19/00;(IPC1-7):H03K19/00 主分类号 H03K19/00
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