发明名称 |
Semiconductor apparatus and data bit inversion |
摘要 |
A semiconductor apparatus may include a first semiconductor chip; and a second semiconductor chip configured to transmit/receive signals to/from the first semiconductor chip. Further, a serializer/deserializer (SERDES) configured to serialize/deserialize input/output signals and a data bit inversion (DBI) logic electrically coupled to the SERDES and configured to perform a data inversion function on input/output data of the SERDES may be arranged in a preset region of any one of the first and second semiconductor chips. |
申请公布号 |
US9530464(B2) |
申请公布日期 |
2016.12.27 |
申请号 |
US201414329568 |
申请日期 |
2014.07.11 |
申请人 |
SK HYNIX INC. |
发明人 |
Byeon Sang Jin |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. A semiconductor apparatus comprising:
a first semiconductor chip; a second semiconductor chip configured to transmit/receive signals to/from the first semiconductor chip; a serializer/deserializer (SERDES) configured to serialize/deserialize input/output signals; and a data bit inversion (DBI) logic coupled to the SERDES and configured to perform a data inversion function on input/output data of the SERDES in response to a data bit inversion signal, wherein the SERDES and the DBI logic are arranged in a preset region of any one of the first and second semiconductor chips, and wherein the first semiconductor chip comprises:
a pad unit configured to input/output data and the data bit inversion signal;a first transmission/reception block configured to transmit/receive signals to/from the pad unit; anda second transmission/reception block configured to transmit/receive signals between the second semiconductor chip and the first transmission/reception block. |
地址 |
Icheon-Si KR |