| 摘要 |
Circuit for recovering the time base in an FFSK or PSK signal demodulator, having a low-pass amplifilter at its input, characterized in that the output of the amplifilter (AP) is connected to a series connection of a keying-integrating circuit (UKC), a level comparator (KP), the first input of a register (R), a combination circuit (UK) with n inputs, and the first input of a phase control and averager circuit (UKF), where the register (R) has n outputs connected to the n inputs of the combination circuit (UK), while that output of the amplifilter (AP) is also connected to a series connection of a voltage comparator circuit (KN), a slope separation circuit (UWZ), a frequency regeneration circuit (URC) for a frequency n times higher than the clock frequency fc and the first input of a divider (D) dividing by n, whereas the output of the divider (D) is the output of the clock frequency fc and is also connected to the second input of the phase control and averager circuit (UKF), while the output of the frequency regeneration circuit (URC) is additionally connected to the second input of the keying-integrating circuit (UKC) and to the second input of (R), and the output of the phase control and averager circuit (UKF) is connected to the second input of the divider (D).<IMAGE>
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