发明名称 |
Image processing memory integrated circuit |
摘要 |
An image processing memory integrated circuit used for a signal processing circuit is disclosed. In the bidirectional prediction, pixel values for two-frame images are stored in a memory cell array. The stored pixel values are read on the basis of address of two-dimensional block. The read pixel values of the two images in the block are added by an adder at an appropriate ratio. The resulting inter-image prediction signal and the interpolation signals are outputted to the outside. In the unidirectional prediction, pixel values for one-frame images are stored in a memory cell array. From the memory cell array, pixel values of two-dimensional block expanded from the above-mentioned block are read. The read pixel value is adaptively added to the pixel value delayed by a predetermined number of pixel from the read pixel value through an adder at an appropriate ratio.
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申请公布号 |
US5528315(A) |
申请公布日期 |
1996.06.18 |
申请号 |
US19940274047 |
申请日期 |
1994.07.12 |
申请人 |
VICTOR COMPANY OF JAPAN, LTD. |
发明人 |
SUGIYAMA, KENJI |
分类号 |
H04N5/92;G06T1/60;G06T9/00;H04N5/46;H04N7/26;H04N7/32;H04N7/46;H04N7/50;(IPC1-7):H04N9/64 |
主分类号 |
H04N5/92 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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